1. Field of the Invention
The present invention is generally in the field of fabrication of semiconductor devices. More particularly, the present invention is in the field of fabrication of heterojunction bipolar transistors.
2. Related Art
In a silicon-germanium (xe2x80x9cSiGexe2x80x9d) heterojunction bipolar transistor (xe2x80x9cHBTxe2x80x9d), a thin silicon-germanium layer is grown as the base of a bipolar transistor on a silicon wafer. The silicon-germanium HBT has significant advantages in speed, frequency response, and gain when compared to a conventional silicon bipolar transistor. Cutoff frequencies in excess of 100 GHz, which are comparable to the more expensive gallium-arsenide based devices, have been achieved for the silicon-germanium HBT.
The higher gain, speed and frequency response of the silicon-germanium HBT are possible due to certain advantages of silicon-germanium, such as a narrower band gap and reduced resistivity. These advantages make silicon-germanium devices more competitive than silicon-only devices in areas of technology where superior speed and frequency response are required.
But as with other transistors, excess base to collector capacitance can detrimentally impact the performance of a silicon-germanium HBT transistor, primarily by reducing its speed. The practical effect of a capacitor is that it stores electrical charges that are later discharged, and the extra time required to charge and discharge the excessive capacitance slows down the transistor. Because the benefits of high gain and high speed can be compromised by excess capacitance, it is a goal of silicon-germanium HBT design to reduce such excess capacitance to a minimum. By keeping the base to collector capacitance low, improved transistor performance is achieved.
Capacitance develops, for example, when two plates made of an electrically conducting material are separated by a dielectric such as silicon dioxide (xe2x80x9cSiO2xe2x80x9d). In general, capacitance is determined by the geometry of the device and is directly proportional to the area of the conductive plates and inversely proportional to the distance, or thickness, separating the two plates. Generally, capacitance is calculated using the equation:
Capacitance (C)=∈0kA/txe2x80x83xe2x80x83(Equation 1)
where ∈0 is the permitivity of free space, k is the dielectric constant of the dielectric separating the two plates, A is the size of the area where the plates overlap one another, and t is the thickness or separation between the two plates. From the Equation (1), it is seen that capacitance could be reduced by the presence of a dielectric with a lower dielectric constant k between the two plates. Alternatively, increasing the separation distance between the two plates, i.e. making the dielectric thicker, could also reduce the capacitance.
FIG. 1 shows an NPN silicon-germanium HBT structure 100, which is used to describe the base to collector capacitance created by conventional silicon-germanium HBT fabrication processes. Certain details and features have been left out of FIG. 1 which are apparent to a person of ordinary skill in the art. Structure 100 includes, among other components, intrinsic collector 134, silicon-germanium base 122, and emitter 120. In exemplary structure 100, intrinsic collector 134 is N type single crystal silicon which can be deposited epitaxially using a reduced pressure chemical vapor deposition (xe2x80x9cRPCVDxe2x80x9d) process. Silicon-germanium base 122 is P type silicon-germanium single crystal deposited epitaxially in a nonselective RPCVD process.
By way of background, because of the nonselective RPCVD process utilized to grow a silicon-germanium layer, the silicon-germanium base as well as other silicon-germanium regions are formed concurrently. The segments of the silicon-germanium layer formed over field oxide region 140 and field oxide region 142 are polycrystalline silicon-germanium and are referred to in this application as polycrystalline silicon-germanium segment 170 and polycrystalline silicon-germanium segment 172. The segment of the silicon-germanium layer that is formed on top of intrinsic collector 134 and extrinsic collector regions 130 and 132, and between field oxide regions 140 and 142 forms the base region of the SiGe HBT and is single-crystal silicon-germanium and is referred to as base 122 or single-crystal silicon-germanium base 122 in the present application.
Polycrystalline silicon-germanium segment 170 and polycrystalline silicon-germanium segment 172 do not function as part of the base of the silicon-germanium HBT but are electrically connected to the base. Situated above base 122 is emitter 120, which forms a junction with base 122 and comprises N type polycrystalline silicon. Extrinsic collector region 130 and extrinsic collector region 132 are situated on each side of intrinsic collector 134. Dielectric sections 126 provide electrical isolation to emitter 120 from base 122. The interface between single-crystal silicon germanium base 122 and intrinsic collector 134, and the interface between single-crystal silicon germanium base 122 and emitter 120 comprise the HBT""s active area. Intrinsic collector 134, single-crystal silicon germanium base 122, and emitter 120 thus form the silicon-germanium HBT.
As further seen in FIG. 1, buried layer 114, which is composed of N+ type material, is formed in semiconductor substrate 110. Collector sinker 112, also composed of N+ type material, is formed by diffusion of heavily concentrated dopants from the surface of collector sinker 112 down to buried layer 114. Buried layer 114 and collector sinker 112 provide a low resistance electrical pathway from intrinsic collector 134 through buried layer 114 and collector sinker 112 to a collector contact (not shown). Deep trench structures 116, field oxide region 140, field oxide region 142, and field oxide region 144 provide electrical isolation form other devices on semiconductor substrate 110. Although structure 100 shows field oxide regions 140, 142, and 144, for the purposes of processing a wafer, field oxide region 140, 142, and/or 144 could be composed of other types of isolation regions, for example shallow trench isolation regions, deep trench isolation, or local oxidation of silicon, generally referred to as xe2x80x9cLOCOSxe2x80x9d.
In a silicon-germanium HBT, base to collector capacitance, also referred to as base-collector capacitance in the present application, is between the base and collector regions and comprises intrinsic and extrinsic components. These components of the base-collector capacitance (xe2x80x9cCbcxe2x80x9d) are seen in FIG. 1. Intrinsic Cbc 154 is between single-crystal silicon germanium base 122 and intrinsic collector 134. Extrinsic Cbc 150 is between polycrystalline silicon-germanium segment 170 and extrinsic collector region 130 and through field oxide region 140, while extrinsic Cbc 152 is between polycrystalline silicon-germanium segment 172 and extrinsic collector region 132 and through field oxide region 142. Again, polycrystalline silicon-germanium segments 170 and 172 are physically and electrically connected to single-crystal silicon-germanium base 122 but do not function as part of the base. Polycrystalline silicon-germanium segments 170 and 172 overlap extrinsic collector regions 130 and 132 and lead to development of the extrinsic components of the total Cbc. The total base to collector capacitance (xe2x80x9ctotal Cbcxe2x80x9d) for the silicon-germanium HBT in structure 100 is the sum of intrinsic Cbc 154, extrinsic Cbc 150 and extrinsic Cbc 152.
Intrinsic Cbc 154 is the junction capacitance inherent in the silicon-germanium HBT device. The capacitance value of intrinsic Cbc 154 is determined by various fabrication parameters in the silicon-germanium HBT device and can only be reduced by altering the fabrication parameters and thus the performance of the device itself. As stated above, extrinsic Cbc 150 and Cbc 152 exist because of the overlap between polycrystalline silicon-germanium segment 170 and polycrystalline silicon-germanium segment 172 with, respectively, extrinsic collector region 130 and extrinsic collector region 132. Polycrystalline silicon-germanium segment 170 and polycrystalline silicon-germanium segment 172 are not part of the SiGe HBT base but are electrically connected to the base.
Extrinsic base to collector capacitance becomes an appreciable portion of total Cbc as device geometries are reduced. The reduction in device geometry is naturally accompanied by a reduction in various geometries, such as the thickness of the field oxide. This xe2x80x9cthinningxe2x80x9d of the field oxide regions lessens the separation, for example, between polycrystalline silicon-germanium segment 170 and polycrystalline silicon-germanium segment 172 from, respectively, extrinsic collector region 130 and extrinsic collector region 132 and therefore increases the level of extrinsic base to collector capacitance.
Various methods aimed at reducing the total Cbc have been introduced. Unfortunately, these methods have not produced the level of capacitance reduction desired or, in other instances, are impractical to implement. For example, one conventional method utilized to try to reduce extrinsic Cbc components employs a relatively thick oxide isolation segment, or LOCOS segment. However, thick LOCOS is difficult to fabricate, particularly in light of the need to accommodate device geometry scaling. Another conventional method involves reducing the area of the base and collector junction, or the base to collector interface, to reduce the intrinsic base to collector capacitance. But altering the device geometry would require otherwise unnecessary alterations in the device fabrication process and would also compromise the device""s performance.
There is thus a need in the art for method of HBT fabrication that reduces the base to collector capacitance. More particularly, there is a need for a method that will limit the total Cbc without adversely impacting the HBT device geometry or diminishing its performance. Further, there is a need in the art for a method which is practical to implement and which will significantly reduce the total Cbc.
The present invention is directed to method for controlling the base to collector capacitance (xe2x80x9cCbcxe2x80x9d) and related structure. The invention results in a heterojunction bipolar transistor (xe2x80x9cHBTxe2x80x9d) with a collector to base capacitance which is lower than that of similar devices fabricated utilizing conventional methods. Further, the invention achieves the reduction without adversely impacting the HBT device geometry or impacting its performance and is practical to implement.
According to one embodiment of the invention, a transistor region comprising a collector region is opened adjacent to an oxide region. In one embodiment of the invention, the oxide region comprises, for example, a field oxide region, a shallow trench isolation, or a LOCOS region. An extrinsic collector region is also formed under the oxide region. Thereafter, a blanket layer of dielectric is deposited over the transistor region and the oxide region. The blanket layer of dielectric can comprise, for example, silicon dioxide, silicon nitride, a low-k dielectric, or other suitable dielectric material. The blanket layer of dielectric is subsequently etched away from the transistor region.
Next, a base region is grown over the collector region. As an example, the base region can comprise single-crystal silicon-germanium grown by a reduced pressure chemical vapor deposition process. Concurrently, a conductive region is formed over the oxide region. The conductive region can comprise, for example, polycrystalline silicon-germanium and is electrically connected to the base region. Following formation of the base region, an emitter region is fabricated on the base region and forms a junction with the base region.
The presence of the dielectric layer on top of the oxide region increases the separation between the conductive region and the extrinsic collector region. The increased separation translates to a reduction in the total base to collector capacitance.